What is polysilicon used for in solar？
Polysilicon is the key high-purity material used to manufacture over 95% of today's solar panels. It is melted and crystallized into ingots, which are then sliced into thin wafers to form the photovoltaic cells that convert sunlight into electricity.
From Sand to Solar
Where standard metallurgical-grade silicon might be 99% pure, the polysilicon used for solar cells requires a staggering 99.9999% purity, often referred to as "6N" or six-nines purity. This intensive purification process is the single most energy-intensive step in solar panel production, historically accounting for up to 40% of the total energy cost to manufacture a panel, though this figure has been dropping steadily with new technologies.
The first major step is transforming quartzite into metallurgical-grade silicon (MG-Si). This is done in a submerged-arc electric furnace at temperatures exceeding 2,000 degrees Celsius (°C). In this furnace, a mixture of quartzite and carbon materials (like coal, coke, or wood chips) undergoes a carbothermic reduction. The carbon reacts with the oxygen in the quartz, releasing carbon dioxide (CO₂) and leaving behind molten silicon, which is about 98-99% pure. However, this silicon is still packed with impurities like iron, aluminum, and calcium, making it useless for electronics or high-efficiency solar cells. For every 1,000 kilograms (kg) of raw materials, this process yields roughly 300 to 400 kg of MG-Si.
The major advantage is temperature; the FBR process operates at a lower 600-700 C, which can reduce energy consumption by 50-60% compared to the traditional Siemens method. This directly translates to a lower carbon footprint and a 10-15% reduction in the final production cost of the polysilicon. As of 2023, FBR-produced polysilicon accounted for nearly 20% of the global market, a share that is projected to grow to over 35% by 2030.
The global production of polysilicon specifically for solar has skyrocketed, from about 500,000 metric tons in 2019 to over 1.2 million metric tons in 2024, driven by a 70% drop in polysilicon prices over the same period. This massive scale-up and cost reduction are primary reasons why the price of solar panels has fallen by over 80% in the last decade, making solar energy the cheapest source of electricity in history for many parts of the world.
Making the Ingots
The choice between them impacts the wafer's atomic structure, with multicrystalline silicon (mc-Si) consisting of numerous smaller crystals and monocrystalline silicon (mono-Si) being a single, continuous crystal. This structural difference leads to a typical 1-2% absolute efficiency gap in the final solar cell, with high-quality mono-Si cells now routinely achieving conversion efficiencies above 23% in mass production, compared to 18-21% for advanced mc-Si. The global market share for monocrystalline technology has surged dramatically, from about 40% in 2018 to dominating the market with over 95% of new production in 2024, driven by its superior performance and decreasing cost differential.
The furnace heats the silicon to a temperature just above its melting point of 1,414 C, creating a molten bath. The key phase is controlled cooling: the temperature is meticulously lowered from the bottom of the crucible upwards at a rate of about 5 to 10 C per hour. This slow, directional cooling encourages crystals to nucleate at the bottom and grow vertically, forming a solid block composed of multiple large crystal grains. A standard ingot produced this way, often called a G1-sized ingot, weighs between 450 and 550 kg and has dimensions of about 840mm x 840mm x 300mm. The entire heating and cooling cycle is energy-intensive, taking roughly 50 hours to complete.
The seed is then pulled upward very slowly, at a rate of 0.5 to 2.0 millimeters per minute, while being rotated simultaneously at a speed of 5 to 20 rotations per minute. The silicon from the melt freezes onto the seed, copying its single-crystal structure. This results in the growth of a cylindrical ingot known as a "boule." A modern large-capacity CZ furnace can pull a single boule weighing over 400 kg with a diameter of 300mm in a cycle lasting 80 to 100 hours. The cost of producing a monocrystalline ingot is typically 10-15% higher than a multicrystalline one due to the longer process time, lower throughput, and the cost of the high-purity seed crystal.
Slicing into Wafers
The drive for cost reduction has relentlessly focused on this process, leading to two key improvements: making wafers thinner and cutting them with less waste. A decade ago, a standard wafer thickness was 200 microns (μm), but today, the mainstream is 150 μm, with leading manufacturers experimenting with wafers as thin as 130 μm. This 25% reduction in thickness directly increases the number of wafers produced per ingot, boosting factory output and reducing silicon cost per wafer by approximately 15%.
Parameter | Traditional Slurry Sawing (Pre-2015) | Modern Diamond-Wire Sawing (Current Standard) |
Cutting Mechanism | Steel wire carries abrasive slurry (SiC powder) | Steel wire with embedded diamond particles |
Wire DiameterDiameter | 120-140 μm | 50-60 μm |
Kerf Loss (Width) | 150-180 μm | 40-50 μm |
Silicon Utilization | ~50% | ~65% |
Cutting Speed | 0.3-0.5 mm/min | 1.5-2.0 mm/min |
Wafer Thickness | 200-220 μm | 150-160 μm |
The revolutionary shift came with the full adoption of diamond-wire sawing, which now accounts for over 95% of global solar wafer production as of 2023. This technology replaced the older, messier slurry-based process. Instead of using a simple steel wire to carry an abrasive slurry of silicon carbide (SiC) powder, the diamond-wire method uses a high-tension piano wire whose core is plated with microscopic, synthetic diamond particles. This single change had a monumental impact. The cutting width, or kerf, was reduced from a massive 180 μm to just 50 μm or less. This 70% reduction in kerf width single-handedly decreased silicon waste by a similar percentage.
A single ingot, weighing up to 600 kg, is mounted onto a moving platform. A single spool of diamond wire, often stretching over 1000 kilometers in length, is wound around precisely spaced guides to form a web of thousands of parallel wire segments. The ingot is then pressed against this moving web of wires while a cooling fluid (usually polyethylene glycol) is applied.
The wire web moves at an extremely high speed, typically 10 to 15 meters per second. As the ingot feeds through this web, the diamond-encrusted wires simultaneously cut hundreds of wafers in one continuous operation. A full cycle to slice a G12-size (210mm) ingot into wafers takes approximately 8 to 10 hours.
How Cells Make Power
The core principle is the P-N junction, a boundary created between two layers of silicon that have been chemically doped with different atoms. For a standard P-type cell, which once dominated over 90% of the market, the silicon wafer itself is doped with boron, giving it a positive (P) character. Then, a thin layer on the top surface, about 0.3 to 0.5 microns thick, is infused with phosphorus, creating a negative (N) type layer.
Feature | Standard PERC (P-Type) | TOPCon (N-Type) | HJT (N-Type) |
Typical Efficiency Range | 21.5% - 22.5% | 23.5% - 24.5% | 24.5% - 25.2% |
Annual Degradation Rate | 0.45% - 0.55% | 0.30% - 0.40% | 0.25% - 0.30% |
Temperature Coefficient (%/°C) | -0.34 to -0.40 | -0.30 to -0.34 | -0.24 to -0.28 |
B-O Light-Induced Degradation | Yes (managed) | No | No |
Estimated Capex Premium | Baseline | +10% - 15% | +30% - 40% |
The manufacturing line for a typical Passivated Emitter and Rear Cell (PERC) involves about 12-15 main steps. It starts with texturization, where the smooth wafer surface is etched into a pyramid-like structure using an alkaline solution like potassium hydroxide (KOH) at 70-80 C. This random texture reduces reflection from a high 35% down to about 8-10% by trapping light through multiple bounces. Next, the wafer undergoes phosphorus diffusion in a high-temperature furnace at 800-900 C to form the N-type layer and the P-N junction. The depth of this junction is critical, typically 0.3-0.5 μm; too shallow and contact resistance is high, too deep and blue light response drops. A key step for PERC is the deposition of a passivation layer on the rear side. This is a thin film of aluminum oxide (Al₂O₃), about 5-15 nanometers thick, topped with a 100nm silicon nitride (SiNx) layer.
A single production line can print over 3,000 wafers per hour. The front side uses a silver paste, and a standard M10-size wafer (182mm) requires about 65-75 milligrams of silver. The rear side uses a cheaper aluminum paste. After printing, the cells are fired in an infrared belt furnace at a peak temperature of 700-800 C for just 1-3 seconds. This firing sinters the metal paste, burning off the organic binders and allowing the metal to form a proper electrical contact with the silicon. This step is incredibly delicate; a temperature deviation of just 10-15 C can ruin the contact quality.
Inside a Solar Panel
A single solar cell, producing only about 7.5 watts at roughly 0.7 volts, is practically useless on its own. The true magic happens when dozens of these cells are assembled into a durable, weatherproof package capable of generating useful amounts of power for 25 to 30 years. A standard solar panel is a sophisticated multilayer sandwich, engineered to protect fragile silicon cells from the elements while maximizing light capture and minimizing degradation. The entire assembly is less than 40 millimeters thick, yet it must withstand hail impacts at 50 meters per second, wind loads exceeding 2,400 Pascals, and temperature cycles from -40°C to +85°C. The performance and longevity of a panel are directly determined by the quality of materials used in this lamination process, often accounting for over 60% of the total panel cost beyond the cells themselves.
In a typical 66-cell panel configuration (common for residential use), solar cells are first electrically connected into "strings." Using fully automated tabbing and stringing machines, thin copper wires coated with a solder alloy, called tabbing ribbons, are soldered onto the front and rear busbars of each cell. A modern stringer can connect over 2,000 cells per hour with a placement accuracy of less than 0.1 millimeters. The number of busbars on cells has increased from 2 or 3 a few years ago to 12 to 16 today, which reduces electrical resistance losses within the cell and improves overall efficiency by about 0.3% absolutely.
The core of panel manufacturing is the lamination process, which fuses the layers into a single, solid unit. The standard layer stack, from front to back, is:
· Tempered Glass: The front surface is a 3.0 to 3.2 millimeter thick sheet of low-iron tempered glass. This glass has an anti-reflective coating that increases light transmittance to over 93.5%, compared to about 91.5% for standard glass. Its tensile strength exceeds 50 Megapascals.
· Encapsulant: Below the glass are two sheets of ethylene-vinyl acetate (EVA) or polyolefin elastomer (POE) encapsulant film, each about 0.5 millimeters thick. POE is increasingly preferred for its superior resistance to potential-induced degradation (PID), especially in n-type cells, and now holds over 50% market share in high-quality panels.
· Cell Matrix: The interconnected solar cells are embedded within the encapsulant.
· Backsheet: The rear side is a multilayer polymer backsheet, typically 0.3 millimeters thick, designed to be an electrical insulator and a moisture barrier. A high-quality backsheet will have a water vapor transmission rate of less than 2 grams per square meter per day.
Powering Homes and Businesses
For a typical residential installation, the total installed cost has decreased by over 60% in the last decade, with the average price per watt now hovering around 2.50 to 3.50 for a standard 5-10 kW system. The efficiency of the entire system—from DC power produced by the panels to usable AC power at your utility meter—is a function of individual module performance and design. This "system efficiency" is typically 5-10% lower than the panel's rated efficiency due to losses in wiring, inverters, and other factors.
Modern string inverters, which handle the output of a whole series of panels, boast peak conversion efficiencies of 98-99%. However, this efficiency varies with the load; it can drop to around 97% when the system is operating at only 20-30% of its capacity, such as on a cloudy morning. For a 10 kW system, even a 1% loss in inverter efficiency translates to over 100 kWh of lost electricity generation annually in a sunny climate.
Microinverters, installed on each individual panel, have a slightly lower peak efficiency, typically 96-97%, but they eliminate the "lowest common denominator" effect of string inverters, where shading on one panel can drag down the performance of the entire string. This can lead to a 5-12% increase in overall energy harvest in partially shaded conditions. The inverters also perform Maximum Power Point Tracking (MPPT), a continuous electronic search for the ideal voltage and current combination to extract the absolute maximum power from the panels, which can fluctuate with temperature and irradiance. A high-quality MPPT algorithm can improve energy yield by up to 2% compared to a basic one.
The racking system, which secures the panels to the roof or ground, must be engineered to withstand specific wind loads, often exceeding 145 km/h, and snow loads of up to 50 kg per square meter. The DC and AC wiring, with cross-sections typically between 6 mm² and 10 mm², is sized to keep voltage drop below 1.5%, preventing significant power loss over the distance to the inverter.