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Can Solar Panels Reach 100% Efficiency | Limits, Physics, Technology

Restricted by the thermodynamic limit (Shockley-Queisser limit of about 33%), single-junction silicon cells are difficult to reach 100%.

Multi-junction cell laboratory efficiency has reached 47.6%; through tandem design, reducing recombination loss, and spectral separation, efficiency can be improved.



Limits

Physical Sticking Point

The reason why single-layer silicon cells are restricted to the 29.4% theoretical limit (S-Q limit) is that semiconductor materials have a threshold named "bandgap." For monocrystalline silicon, this bandgap width is fixed at 1.12 eV; only photons with energy greater than this value can excite electrons to produce current.

· Under standard AM1.5G spectral conditions (that is, sunlight traveling through 1.5 times the thickness of the atmosphere, radiation intensity about 1,000 W/), the ideal bandgap should be 1.34 eV, at which the corresponding peak efficiency is 33.7%.

· The 1.12 eV bandgap of silicon material leads it to naturally miss about 19% of long-wave infrared light energy; these photons directly pass through the cell piece like they are transparent, unable to produce any charge.

· If the bandgap is adjusted too high (for example, 2.0 eV), although it can capture high-energy photons, it will lose most of the visible light region, leading to a sharp drop in current; if adjusted too low, it will lead to a serious decline in open-circuit voltage (Voc).

Energy Cannot Be Consumed

Even if the energy of a photon exceeds 1.12 eV, the extra energy cannot be turned into electricity. The energy of a 400 nm blue-violet photon is about 3.1 eV; when it hits a silicon atom, the extra 1.98 eV (about 64% of its own energy) will convert into lattice vibration, which is heat, within just a few picoseconds due to the "thermalization effect."

· This thermalization loss accounts for as high as 33% to 35% in single-junction cells, which is the biggest obstacle to efficiency breaking 40%.

· According to statistics, in the sunlight energy incident on the cell piece, about 47% of the portion is wasted because the energy and bandgap do not match.

· Currently, laboratories are trying to use "hot carrier" technology, attempting to extract the energy before it turns into heat, but even in a femtosecond laser laboratory environment, the collection efficiency of such carriers is difficult to maintain above 1%.

Turned Into Heat

Under direct noon sunlight, the surface temperature of photovoltaic modules is usually 25°C to 30°C higher than the ambient temperature. The open-circuit voltage (Voc) of silicon cells is extremely sensitive to temperature; for every 1°C increase in temperature, the voltage usually drops by 2.0 mV to 2.2 mV.

· For a monocrystalline silicon cell with a Voc of 0.7 V, when the temperature rises from 25°C to 65°C, the voltage loss ratio is about 12.5%.

· The fill factor (FF) also decreases accordingly, usually falling from 0.82 to around 0.75, leading to the overall output power showing a negative offset of 0.35%/°C.

· A module with a nominal power of 600 W often has a measured power of only just over 500 W on a 70°C roof; nearly 100 W of potential electrical energy vanishes into thin air in the high temperature.

Internal Electricity Leakage

Even if photons successfully convert into electron-hole pairs, they face the risk of disappearing by "recombination" on the way to the wires. This loss is mainly divided into radiative recombination, Auger recombination, and defect recombination (SRH). Under high-concentration doping or strong light, Auger recombination dominates; before the electron even runs out of the cell piece, three carriers collide with each other, and the energy cancels out.

· Advanced TOPCon cells, by growing a 1-2 nm ultra-thin silicon oxide and doped polysilicon layer on the back, reduce the surface recombination velocity (SRV) to below 10 cm/s, barely lifting the efficiency from PERC's 23% to 25.5%.

· Series resistance (Rs) is also a major factor, including silicon wafer resistance itself and metal grid line contact resistance; even if the resistance is only 0.5 Ω·cm², under high-current operation, it will cause 2% to 3% power loss.

· Current silver paste consumption is about 8-10 mg/W; although it increases conductivity, the shading area of silver finger lines accounts for 3% to 5% of the module's front surface area, which is another hard current loss.

Surface Reflection

The natural reflectivity of a silicon surface is as high as 35% or more; if not processed, one-third of the light will bounce away like reflecting in a mirror. To reduce the reflectivity to below 2%, manufacturers must carve billions of micron-level "pyramid" textures on the silicon wafer surface through alkali etching.

· The textured structure allows light to undergo secondary or multiple reflections on the surface, increasing the probability of absorption; this light-trapping effect can increase short-circuit current (Isc) by about 15% to 20%.

· Combined with silicon nitride (SiNx) anti-reflection coating, the effective absorption band can be extended to 400 nm-1100 nm, but for light incident at large angles (such as early morning or evening), reflection loss still increases by 5% to 10%.

· The tempered glass cover plate on the module surface itself has a 4% transmission loss; even with an AR coating, long-term wind and sand wear will cause the transmittance to drop by about 0.1% every year.

Ceiling Height

By stacking materials with different bandgaps together, high-energy photons are absorbed by large-bandgap materials, and low-energy photons pass through to be absorbed by small-bandgap materials.

· The theoretical limit of triple-junction cells (such as InGaP/InGaAs/Ge) can reach 63.8%; under 500 times concentrated light conditions, the laboratory record has already reached 47.1%.

· Currently, the most promising civilian solution is the "perovskite/silicon" tandem; perovskite is responsible for the high-energy band of 1.7 eV, and silicon is responsible for the low-energy band of 1.12 eV; its theoretical upper limit is 42.5%, and laboratory efficiency has broken through 34%.

· The current ordinary module levelized cost of electricity (LCOE) is about 0.1-0.2 yuan/kWh, while the four-junction cells used in space stations are more than 1000 times higher in cost; for every 1% increase in efficiency, if it cannot cover its increased manufacturing cost within a 25-year lifespan, this "high efficiency" is meaningless commercially.



Physics

Energy Threshold

For monocrystalline silicon, the minimum energy required to kick out an electron is called the bandgap, and the value is fixed at 1.12 eV. In the spectrum of standard ground sunlight (AM1.5G, irradiance 1000 W/), about 20.2% of photons have energy lower than 1.12 eV; these long-wave photons hitting the silicon wafer are just like they are transparent, generating no photovoltaic effect at all, and the energy absorption rate is 0.

As for those high-energy photons with energy higher than 1.12 eV, such as ultraviolet light with a wavelength of 400 nm (energy about 3.1 eV), their extra 1.98 eV of energy does not turn into current, but rather, in an extremely short 10 to the power of negative 12 seconds (picosecond) magnitude, converts into thermal energy through lattice collisions. This thermalization loss caused by energy mismatch accounts for about 33% of the total energy in a single-layer silicon cell, which is the first big pit that cannot be avoided in physics.

Light Cannot Be Caught

The absorption coefficient of silicon material varies drastically with wavelength; for infrared light with a wavelength close to 1100 nm, the absorption capacity of silicon is extremely weak, requiring hundreds of microns in thickness to absorb more than 90% of photons. Currently, to save costs, the silicon wafer thickness has been reduced from 180 μm to 130 μm or even thinner, which leads to an increase in the escape rate of long-wave photons by 3% to 5%.

· Reflection loss: The reflectivity of a bare silicon surface exceeds 30%; even with the use of silicon nitride (SiNx) anti-reflection coating and pyramid texture light-trapping technology, there are still 1% to 2% of photons directly bounced away.

· Shading loss: To export current, metal silver paste grid lines must be laid on the front of the cell; these grid lines will shade about 2.5% to 4% of the effective light-receiving area.

· Quantum efficiency: In specific wavebands, one photon might not produce an effective electron-hole pair; this deviation in external quantum efficiency (EQE) usually leads to about 2% of current loss.

Particle Movement

After electrons are excited, they must run out of the p-n junction and enter the wire before being "recombined" and annihilated. This process involves the diffusion length and lifetime of carriers. In high-quality N-type monocrystalline silicon, the minority carrier lifetime is usually between 1 millisecond and 10 milliseconds, and the corresponding diffusion length is about 300μm to 1000μm.

· Recombination rate: Surface recombination velocity is an important indicator affecting efficiency; TOPCon cells after passivation treatment can drop to below 10 cm/s.

· Mobility: The moving speed of electrons in the silicon lattice is limited by scattering effects.

· Built-in electric field: The intensity of the built-in electric field formed by the p-n junction directly determines the efficiency of charge separation; usually, this voltage difference (open-circuit voltage Voc) is difficult to exceed 0.75 V.

Internal Loss

When the cell is working, the flow of internal charges will produce resistance loss (Joule heat). This includes the bulk resistance of the silicon wafer itself, the contact resistance of metal grid lines, and the resistance of external busbars. To reduce resistance, manufacturers must increase the use of silver paste, but this will in turn increase costs and shade sunlight, forming a physical game.

Loss Type

Energy Proportion (Estimate)

Physical Reason

Low-energy photon penetration

18% - 20%

Photon energy lower than bandgap (1.12 eV)

High-energy photon thermalization

32% - 35%

Extra energy converted to lattice vibration

Carrier recombination

3% - 8%

Electron-hole pairs combine before reaching electrodes

Resistance Ohmic loss

1% - 3%

Metal grid lines and silicon wafer resistance heating

Surface reflection shading

3% - 5%

Glass reflection and silver finger line shading

Efficiency Accounting

Through thermodynamic derivation, we can calculate the performance of different materials in an ideal state. Single-layer cells, due to being limited by a single bandgap, have a clear efficiency "ceiling." If you want to improve efficiency, you must change the bandgap width of the material or adopt a multi-layer stacked structure.

· Single-junction limit: The S-Q limit gives 33.7% (under 1.34 eV bandgap), while the actual theoretical limit of silicon is 29.4%.

· Fill Factor (FF): This is an important parameter to measure cell quality; currently, the FF of top cells has reached 83% to 85%, and the room for further improvement is extremely small; every 0.5% increase requires extremely high process precision.

· Voltage loss: Theoretically, the Voc limit of silicon cells is about 0.8V; in actual mass production, reaching 0.73V is already an industry-leading level.

Physical Upper Limit

Even without considering reflection, impurities, and resistance, the second law of thermodynamics also stipulates the dissipation of energy conversion. According to the Carnot efficiency limit, obtaining energy from the sun, a 5800K heat source, in a 300K room temperature environment, the highest conversion efficiency will not exceed 95%. And considering the increase in photon entropy, the actual physical upper limit (Landsberg Limit) is locked at around 93.3%.

By stacking materials with bandgaps of 1.9 eV, 1.4 eV, and 0.7 eV respectively, the spectral utilization can be greatly improved. Currently, the laboratory efficiency of triple-junction cells under 500 times concentrated light has reached 47.1%, but this has already broken away from the scope of ordinary silicon-based physics and entered the more complex field of III-V compound semiconductors. For ordinary civilian modules, the 29.4% determined by physical laws is like a wall; all technical optimizations are just infinitely approaching this wall, but never able to penetrate it.

Technology

Structure Upgrade

Current mainstream cell technology is comprehensively shifting from PERC to TOPCon (Tunnel Oxide Passivated Contact). Traditional PERC cells, due to high carrier recombination loss in the back metal contact area, have a mass production efficiency that is difficult to break through 23.5%. TOPCon technology, by growing an ultra-thin silicon dioxide tunnel layer of only 1.5 to 2.0 nanometers on the back of the cell, combined with a doped polysilicon layer of about 20 nanometers, achieves excellent passivation effects.

In actual mass production data, the Voc of TOPCon cells has increased from 685 mV in the PERC era to over 730 mV. Under the same light intensity, the potential difference of a single cell piece has increased by about 6.5%. Current average mass production efficiency of first-tier manufacturers for TOPCon has stabilized between 25.8% and 26.2%; compared to traditional technology, each module can generate about 5% to 8% more total power over a 25-year lifespan.

Front Side No Shading

To push the photogenerated current (Isc) to the limit, BC (Back Contact) technology directly removes all metal grid lines on the front of the cell. Traditional cell pieces have 9 to 16 main busbars and hundreds of fine fingers on the front; these silver paste lines will shade about 3% to 5% of the incoming sunlight. BC technology, through extremely complex micro-nano processing processes, transfers all positive and negative electrodes to the back of the cell, making the front light-receiving area reach 100%.

The realization difficulty of this technology lies in the interdigitated arrangement of the positive and negative electrodes on the back, which requires extremely high alignment precision to prevent short circuits. Currently, the mass production efficiency of IBC cells based on N-type substrates has exceeded 26.5%, and its short-circuit current density has increased from 40 mA/cm² to above 42.5 mA/cm². Since there is no metal shading on the front at all, the performance of this module in low-light environments is also about 3% higher than that of ordinary modules.

Two-Layer Stacking

Single-junction cells have natural shortcomings in absorption spectra, so "perovskite/crystalline silicon" tandem technology has become the most anticipated dark horse currently. This solution coats perovskite material with a bandgap of about 1.7 eV on top of a crystalline silicon cell with a bandgap of 1.12 eV. The perovskite layer is responsible for swallowing high-energy blue-violet light and converting it into high voltage, while the transmitted infrared light is converted by the crystalline silicon layer at the bottom. This "relay race" type of absorption directly tears an opening in the S-Q limit.

Laboratory data shows that the conversion efficiency record for perovskite/crystalline silicon tandem cells has been refreshed to 33.9%, far exceeding the 29.4% theoretical limit of single-layer silicon cells. If mass production can be realized in the future, for a power station of the same area, the installed capacity can be increased from the current 200 W/ to over 280 W/.

Slicing Technology

Current silicon wafer thickness has quickly thinned from 180μm in the past to 130μm or even 110μm; thinning not only saves about 30% of polysilicon material usage but also shortens the movement path of charges inside the silicon wafer, reducing recombination probability.

· In terms of size: M10 (182 mm) and G12 (210 mm) have become the absolute mainstream; large-size silicon wafers can reduce gap loss during module packaging, increasing module efficiency (Module Efficiency) by about 0.2% to 0.5%.

· Cutting loss: Using extremely fine diamond wire of 30μm to 35μm for cutting has reduced kerf loss (Kerf Loss) by 15%, allowing 2 to 3 more silicon wafers to be cut from each kilogram of silicon material.

· Light-trapping treatment: Using black silicon technology (Black Silicon) combined with atomic layer deposition (ALD) technology to create nano-scale pits on the silicon wafer surface, squeezing the average reflectivity of incident light from 2% down to below 0.5%.

Paste Reduction

Silver paste is the highest-cost part of the cell besides the silicon wafer, accounting for about 10% to 15%. To reduce the levelized cost of electricity (LCOE), the industry is promoting silver-coated copper (Ag-coated Cu) technology or electroplated copper technology. HJT (heterojunction) cells, because they need to be processed in a low-temperature environment, have a high dependence on silver paste; the silver consumption per piece once reached as high as 200 mg.

By adopting fine-line printing technology below 15 μm and silver-coated copper paste, current silver consumption per piece has dropped to around 80 mg, and the efficiency has almost no loss. Electroplated copper technology is even more thorough, directly replacing the precious metal silver with low-priced copper; this not only eliminates the resistance heat loss of silver grid lines (the conductivity of copper is close to that of silver) but also compresses the grid line width to around 10μm. This process progress has reduced the internal Ohmic loss of the cell by about 0.3%, while increasing effective light intake by about 1%, achieving dual optimization of cost and power.

High-Efficiency System

Current bifacial modules (Bifacial) utilize the light reflected from the ground absorbed by the back side to obtain an extra power generation gain of 5% to 25% (Bifacial Gain). Combined with single-axis tracking brackets, the modules can adjust their angle all day like sunflowers, ensuring sunlight is always incident at an angle close to 90 degrees vertical, which is 15% to 20% higher in annual power generation than fixed brackets.

To solve the current mismatch loss inside the module, manufacturers generally adopt half-cut (Half-cut) technology. Cutting a complete cell piece into two halves reduces the working current by half. According to Joule's law, internal resistance loss will be reduced to 1/4 of the original. This design not only increases module power by 5W to 10W but also significantly reduces the risk of burnout caused by the hot spot effect, making the power output stability of the system under partial shadow shading improve by about 30%.