How solar cells work step by step

First, the P–N junction absorbs photons to excite electrons in the silicon wafer, and then, under the action of the built-in electric field, the electrons are driven to flow in a directional manner.

Currently, the mainstream monocrystalline silicon cell efficiency is approximately 20% to 22%.

Finally, these charges are exported through metal wires to form direct current (DC) for external loads, achieving efficient conversion of clean energy.

Absorption and Excitation

Layer Light Capturing

Solar radiation intensity under Standard Test Conditions (STC) on the Earth's surface is set at 1,000 W/m².

The reflectivity of bare silicon wafer surfaces to light is as high as 35% to 45%. To reduce this energy loss, a silicon nitride (SiNx) anti-reflection coating with a thickness of 70 nm to 90 nm needs to be deposited on the cell surface.

The refractive index of this layer is usually set between 1.9 and 2.1, using the principle of thin-film interference to reduce the reflectivity of specific wavebands (mainly visible light around 600 nm) to below 2%.

In addition to chemical coating, the silicon wafer surface will be created with pyramid micro-textures with a height of 3 to 5 microns through chemical acid-base etching.

This textured structure allows incident light to produce multiple reflections on the surface, thereby increasing the optical path to more than 3 times the original, allowing more than 90% of effective photons to enter the interior of the silicon wafer.

Silicon-based Light Absorption

After photons enter the silicon wafer, their energy must overcome the 1.12 electron volt (eV) bandgap of monocrystalline silicon to be effectively utilized.

Light with wavelengths between 300 nm and 1100 nm in the solar spectrum is the main contributor to power generation.

Short-wavelength blue-violet light (approx. 400 nm) has higher energy and is absorbed at a depth of less than 1 micron upon entering the silicon wafer surface;

while long-wavelength infrared light (approx. 1000 nm) has strong penetration and needs to travel 100 microns or even further to be captured.

The thickness of silicon wafers used in mainstream N-type cells has currently been reduced to 130μm to 150μm. This thickness ensures that more than 95% of infrared photons are absorbed while effectively controlling material costs at about 0.5 to 0.8 yuan per piece.

The purity requirements for silicon wafers are extremely high, usually reaching 9N to 11N levels (i.e., above 99.9999999%), to ensure fewer defects inside the crystal lattice and reduce the abnormal disappearance of carriers during movement.

Particle Awakening

When a photon hits a valence band electron in a silicon atom, if the photon energy is greater than 1.12 eV, the electron is pushed into the conduction band, producing a negatively charged free electron and a positively charged hole. This is the excitation process of photogenerated carriers.

Internal Quantum Efficiency (IQE) in the 400nm to 900nm band can usually reach over 98%, meaning almost every absorbed photon can produce a pair of carriers.

However, short-wave photons with energy far higher than 1.12 eV (such as 3.1 eV ultraviolet light), after exciting electrons, the extra 1.98 eV of energy will rapidly convert into thermal energy, leading to lattice vibration and phonon generation.

This is the main energy loss item causing the approx. 33.7% theoretical efficiency limit (Shockley-Queisser Limit) of solar cells.

For every 1℃ increase in temperature during cell operation, its Open Circuit Voltage (Voc) decreases by about 2 mV, leading to a negative growth of 0.3% to 0.4% in overall output power.

Lifetime Competition

For current mainstream TOPCon cells, the Minority Carrier Lifetime is usually required to be between 1 ms and 10 ms, which determines that the diffusion length of carriers in the bulk must be greater than 2 times the wafer thickness (approx. 300μm to 500μm).

To prevent surface recombination, the back of the cell is covered with a 10 nm to 20 nm aluminum oxide (Al2O3) or silicon dioxide (SiO2) passivation layer, controlling the Surface Recombination Velocity (SRV) below 10 cm/s.

Energy Loss

Long-wave infrared light below 1.12 eV (wavelength > 1100 nm) will directly penetrate the silicon wafer or be absorbed by the back aluminum film and converted into heat due to insufficient energy; this part of the loss accounts for about 19% of total incident energy.

In the excitation process, Thermalization Loss is the biggest obstacle.

For example, for a 2.5 eV blue light photon, only 1.12 eV is used to generate electricity, and the remaining 1.38 eV is all dissipated as heat.

To address this issue, Multi-junction cells by stacking materials with different bandgaps (such as Perovskite tandem cells, with a bandgap of about 1.7 eV), attempt to capture high-energy photons in segments, thereby pushing theoretical conversion efficiency to a new height of 35% to 43%.

In current monocrystalline silicon production, by optimizing the diffusion process to control the emitter sheet resistance between 120 Ω/sq and 150Ω/sq, resistance loss can be reduced by about 0.5% while ensuring light absorption.

Separation and Separation

Creating Electric Field

In a high-temperature diffusion furnace at 820℃ to 900℃, Phosphorus Oxychloride (POCl3) gas reacts with the silicon wafer surface, forcing phosphorus atoms into the silicon lattice to form an N-type emitter with a depth of approx. 0.3μm to 0.5μm.

At this time, the doping concentration gradient on both sides of the interface is extremely high. The phosphorus atom concentration in the N-region can reach 10²⁰ atoms/cm³, while the boron atom concentration in the P-region substrate is maintained at around 10¹⁶ atoms/cm³.

Due to the concentration difference, free electrons from the N-region diffuse to the P-region, and holes from the P-region diffuse to the N-region. This particle migration leaves a layer of positively charged donor ions and negatively charged acceptor ions at the interface, forming a space charge region with a thickness between 0.1μm and 0.8μm.

Important Physical Parameter Reference: The built-in electric field intensity established in this region is usually in the order of 10⁴ V/cm, and the built-in potential difference (Vbi) produced is between 0.6V and 0.7V.

Defining Boundaries

The direction of the electric field within the space charge region is from the N-region to the P-region, forming a difficult-to-surmount barrier that effectively prevents separated charges from flowing back.

When photogenerated carriers are produced near the P-N junction, negatively charged electrons are subject to an electric field force moving toward the N-region, while positively charged holes are pushed toward the P-region.

To ensure charges complete the crossing within a microsecond-level lifetime of 1ms to 10ms, the recombination current density inside the silicon wafer must be controlled below 10⁻¹² A/cm².

For N-type TOPCon cells, by introducing an ultra-thin silicon dioxide (SiO2) layer with a thickness of only 1.2 nm to 1.5 nm on the back, combined with a doped polysilicon layer of about 20 nm, selective carrier passage can be achieved using the quantum tunneling effect, drastically lowering the surface recombination rate from 100 cm/s to 1cm/s to 5 cm/s.

Interface Loss Reference Data: If the saturation current density (J0) of this boundary increases by 10 times, the open circuit voltage (Voc) of a single cell will drop by about 60 mV, corresponding to an overall conversion efficiency loss of about 1.5% to 2.2%.

Driving Electrons

In monocrystalline silicon, as minority carriers in the P-region, the diffusion length of electrons usually needs to reach 400μm to 600μm, far exceeding the current physical thickness of 150μm for silicon wafers, to ensure more than 99.5% of photogenerated electrons can successfully reach the N-region collector.

By optimizing the doping process to control the emitter sheet resistance within the range of 120 Ω/sq to 160Ω/sq, a balance can be achieved between reducing lateral resistance loss and decreasing surface recombination.

In actual load operation, this potential gradient ensures the cell can output a Fill Factor (FF) as high as 80% to 85%, reflecting that internal resistance and carrier recombination losses are suppressed to extremely low levels.

Preventing Backflow

To block charges from returning to an equilibrium state during transport, modern cell structures add a Back Surface Field (BSF) or passivated contact layer on the back.

For PERC cells, a local aluminum back surface field is used to generate a co-directional electric field, reflecting electrons near the back toward the P-N junction and preventing them from undergoing 100% quenching recombination at the back metal electrode.

This potential design reduces recombination losses on the back by about 85%. Additionally, by adjusting the layout spacing of busbars to 1.5 mm to 2.2 mm, shortening the lateral movement distance of carriers on the surface layer can control the series resistance (Rs) below 0.3 Ω.

Under standard light intensity, the short-circuit current (Jsc) per square centimeter can stabilize between 40 mA and 42 mA, representing extremely high transmission fidelity throughout the process from charge separation to final outflow.

Energy Balance Explanation: In a working environment of 25℃ to 50℃, through such strict potential gradient management, the non-radiative recombination ratio inside the cell is limited to within 5% of the total excitation, ensuring efficient directional flow from light energy to electrical energy.

Conversion

Converting to Electricity

The voltage output by a single cell is usually between 0.6V and 0.7V. To reach the voltage levels required for power transmission, 60, 72, or 78 cells need to be connected in series.

Taking a 72-cell monocrystalline module of 182 mm size as an example, its open circuit voltage (Voc) is usually set between 49 V and 51 V.

When multiple modules are connected in series outdoors via DC cables to form a "string", the system voltage will rapidly increase to 1000V or even 1500V.

Compared to traditional 1000V systems, 1500V systems can reduce DC side line losses by more than 50% and reduce DC cable usage by about 20% to 30%.

During the conversion process, Maximum Power Point Tracking (MPPT) technology scans the current-voltage (I-V) curve every 1 to 5 seconds to find the current power peak point.

Currently, the static MPPT tracking efficiency of high-efficiency inverters has reached over 99.9%, ensuring the system maintains a conversion output of over 98% within 0.5 seconds of cloud shading or intense light fluctuations.

Deducting Losses

The junction box is usually configured with 3 Schottky bypass diodes, with a forward voltage drop of about 0.4V to 0.7V.

When local shadow shading reaches 10%, the diode will skip the obstructed cell cluster to prevent the hot spot effect, but this operation will lose about 33% of the voltage output for that string.

DC cable wire diameters are usually selected as 4mm² or 6mm² photovoltaic-specific copper wire, with DC resistance at 20℃ of approx. 4.61Ω/km to 5.09Ω/km.

If the string length exceeds 50 meters, the voltage drop on the cable should be controlled within 1% to 2% of the total voltage; otherwise, the resulting thermal loss will lead to a 0.5% to 1.5% decrease in annual power generation.

Additionally, the contact resistance of MC4 connectors between modules is usually required to be below 0.5 mΩ. If resistance rises to 10 mΩ due to improper construction, the contact will generate a constant thermal power of 1 W at 10 A current, increasing the risk of melting.

Transforming Voltage and Frequency

The inverter, acting as a transit station in the conversion stage, uses IGBT (Insulated Gate Bipolar Transistor) to switch at high frequencies of 16 kHz to 20 kHz, converting unstable DC power into 50 Hz or 60 Hz sine wave AC power.

Currently, the maximum conversion efficiency of string inverters has exceeded 99%, while the Euro Efficiency or CEC Efficiency, which better reflects real operating conditions, usually remains around 98.5%.

In the inverter stage, about 1% to 1.5% of energy is converted into heat, causing internal heat sink temperatures to rise to 50℃ to 65℃.

To ensure power quality at the grid end, the Total Harmonic Distortion (THD) of the current output by the inverter must be controlled below 3%.

In high-altitude or high-temperature environments, the inverter will trigger power derating protection; for example, for every 1℃ increase in ambient temperature, output power may be forcibly reduced by 2% to 5% to ensure that fragile modules like internal electrolytic capacitors reach a design life of 10 to 15 years.

Stabilizing Output

Light-Induced Degradation (LID) mainly occurs within the first 100 hours of module operation. The LID loss of P-type monocrystalline cells is usually between 1.5% and 2.5%, while gallium-doped wafers or N-type cells can reduce such losses to below 0.5%.

Potential-Induced Degradation (PID) is a more serious threat. Since the system voltage is as high as 1000 V, the strong electric field between the frame and the cell will lead to charge leakage, which, in severe cases, can cause power to drop by more than 30% within six months.

Modern conversion systems use the PID recovery function integrated into the inverter to apply a reverse bias to the module at night, pushing the outflowing ions back into place, thereby stabilizing the annualized power degradation rate between 0.4% and 0.55%.

This means a system with a nominal power of 100 kW can still maintain an output capacity of 83 kW to 85 kW after 25 years, with the overall system Performance Ratio (PR value) usually stabilizing between 75% and 85%.