High-Efficiency Modular Solar Panels | N-Type vs. P-Type Silicon Cells

N-type silicon cell efficiency 25%+ (first-year degradation <1%), P-type 22%-24% (degradation 1-2%).

Choose N-type for high-return projects, P-type for cost sensitivity, focus on temperature coefficient optimization.

N-Type Silicon Cells

N-type silicon cells use phosphorus-doped silicon wafers, with electrons as majority carriers, achieving higher efficiency than P-type.

Laboratory efficiency 26.1% (NREL), TOPCon mass production 25-25.5%, HJT 24.5-25%.

Light-induced degradation (LID) <0.5% (P-type 2-3%), temperature coefficient -0.3%/°C (P-type -0.35 to -0.4%/°C).

2023 global N-type capacity increased by 300% year-on-year, projected to occupy 55% market share by 2025 (PV Tech).

Mainstream technologies: TOPCon, HJT, IBC.

Working Principle

How Phosphorus Doping Makes Electrons the Majority

Silicon atoms have 4 valence electrons, forming a stable crystal structure.

During manufacturing, silicon wafers are treated with phosphorus-containing gas (e.g., phosphine PH₃) at high temperatures, allowing phosphorus atoms (with 5 valence electrons) to randomly replace some silicon atoms.

Phosphorus has one more valence electron than silicon. This extra electron is not bound by covalent bonds and requires very little energy to detach from the atom, becoming a free electron.

When the phosphorus atom concentration reaches 10¹⁵-10¹⁶ per cm³ (about one part per million), the number of free electrons in the silicon wafer far exceeds the number of holes ("empty spaces" left behind when electrons leave), making electrons the majority carriers and holes the minority carriers.

Comparison with P-type silicon cells: Boron (a 3-valent element) doping makes holes the majority carriers.

However, boron easily combines with oxygen atoms in silicon to form "boron-oxygen complexes" (B-O pairs), which act as recombination centers for electron-hole pairs, leading to efficiency loss.

Phosphorus doping in N-type silicon largely avoids this issue (IEA PVPS 2023 report).

How Important is Long Minority Carrier Lifetime

The minority carrier lifetime in N-type silicon wafers can reach 10-100 milliseconds (Fraunhofer ISE measured data), while P-type silicon wafers are typically only 0.1-1 microseconds—a difference of 10⁴ times.

Why is this critical? When a solar cell operates, photons strike the silicon, generating electron-hole pairs.

These carriers need to "survive" long enough to be collected by the electrodes.

A longer minority carrier lifetime means holes have more time to diffuse to the vicinity of the cell's PN junction before recombining, where they are separated by the built-in electric field and extracted.

Data: Under standard test conditions (STC, 1000W/m² irradiation, 25°C), the recombination loss of N-type cells is 20-30% lower than P-type (NREL 2023).

For example, for the same 1 square meter of silicon, an N-type cell can collect about 0.5 amps more current (assuming a short-circuit current of 7.5A, N-type can reach 8A).

How the Passivation Layer Reduces Electron "Loss"

Taking the most mature TOPCon as an example: First, an ultra-thin silicon oxide (SiO₂) layer is grown on the silicon surface, only 1-2 nanometers thick (about 1/50,000th the diameter of a human hair).

This oxide layer acts like a "sieve"—it's too thick for holes to pass through (blocking recombination), but electrons can "tunnel" through (quantum tunneling effect).

Then, a layer of doped polysilicon (150-200 nm) is deposited on the oxide layer.

Measured effect: After passivation, the surface recombination velocity of the silicon wafer drops from 10³ cm/s for P-type to <10 cm/s (Fraunhofer ISE).

Simply put, where previously 30 out of 100 holes recombined at the surface, now less than 1 does.

What's Special About HJT's Amorphous Silicon Layers

First, coat both sides of the N-type silicon wafer: The inner layer is intrinsic amorphous silicon (i-a-Si: H) (undoped, specifically for passivating dangling bonds), and the outer layer is doped amorphous silicon (n-a-Si: H or p-a-Si: H).

The advantage of amorphous silicon is its low-temperature process (200°C, compared to 800-900°C for PERC), which does not damage the silicon wafer's crystal structure and enables double-sided passivation.

Data shows the surface recombination velocity of HJT is even lower than TOPCon, about <5 cm/s (Meyer Burger lab data).

The trade-off is expensive equipment—amorphous silicon deposition requires magnetron sputtering or PECVD, costing twice as much as a PERC production line.

The Complete Process from Light to Electricity

1. Light Absorption and Carrier Generation: Sunlight (photons) penetrates the anti-reflection coating (ARC) on the cell surface and strikes the N-type silicon wafer. Photons with energy greater than silicon's bandgap (1.1 eV) excite electrons, generating electron-hole pairs.

2. Carrier Separation: The PN junction inside the silicon wafer (typically a shallow junction formed by phosphorus diffusion) has a built-in electric field that pushes electrons toward the N-region surface and holes toward the backside electrode (or vice versa, depending on the structure).

3. Tunneling and Extraction: When electrons reach the N-region surface, they encounter the tunneling oxide layer. They pass through via quantum tunneling into the polysilicon layer and are collected by the silver grid lines on the front side; holes travel through the silicon bulk and are collected by the backside electrode.

4. Current Output: Positive and negative electrodes connect to an external circuit. Electrons flow through the load, performing work, and return to the hole side to complete the cycle.

Why the Temperature Coefficient is Better

N-type silicon has a slightly larger bandgap (1.12 eV) than P-type (effectively smaller due to boron-oxygen complexes) and higher electron mobility (1,350 cm²/V·s vs. 480 cm²/V·s for P-type).

Measured data: The temperature coefficient of N-type cells is -0.3%/°C, while P-type PERC is -0.35 to -0.4%/°C.

In Arizona (where module temperatures often reach 60°C in summer), the power output of N-type modules is about 8-10W higher than P-type (based on a 400W module), resulting in 3-5% more annual energy generation (Enel Green Power U.S. project measured data).

The Secret of Bifacial Power Generation

The bifaciality factor (rear-side efficiency / front-side efficiency) of HJT can reach 95%, TOPCon about 85-90%, while P-type PERC is only 70-75%.

Reason: HJT's amorphous silicon layers cover both sides completely, allowing efficient light absorption from the rear;

Although TOPCon's polysilicon layer is on the back, the oxide layer has good light transmittance.

In a German farm project, the rear side of HJT bifacial modules contributed 22.8% of total power generation (Meyer Burger case study), while P-type PERC contributed only 18%.

Performance Advantages

How Much Higher is the Efficiency Compared to P-type?

In the lab, TOPCon cell efficiency tested by NREL in 2023 reached 26.1%, HJT reached 25.8%, and IBC even touched 26.5% (SunPower Maxeon 6).

In mass production, TOPCon stabilizes at 25-25.5% (Q Cells Q. TRON series), HJT at 24.5-25% (Meyer Burger Glass-Glass), and IBC around 25-26% (historical data from LG Solar).

Compared to P-type PERC, the industry average is only 23-24%, a difference of 1-2 percentage points.

Using phosphorus doping, the minority carrier lifetime (hole survival time) in N-type is 10-100 milliseconds (Fraunhofer ISE measured data), while P-type is only 0.1-1 microsecond—a difference of 10,000 times.

A longer minority carrier lifetime means fewer photogenerated electron-hole pairs recombine before collection, so more are collected.

For example, for the same 1 square meter of silicon, the short-circuit current of N-type can reach 8A, while P-type PERC is typically 7.2-7.5A (NREL STC testing).

The open-circuit voltage (Voc) is also higher: TOPCon can reach 720-730mV, while P-type PERC is only 690-700mV.

The fill factor (FF) is 82-83% for N-type and about 80% for P-type.

Slower Power Degradation Over Time

P-type cells have a chronic problem: power decreases after prolonged light exposure, called light-induced degradation (LID).

In the first few months after installation, power can drop by 2-3% (IEA PVPS 2023 report).

At high temperatures, another wave of degradation can occur (LeTID), causing an additional drop of 3-5%.

LID measured is <0.5% (Fraunhofer ISE), and LeTID is 10-15% lower than P-type.

For instance, Norway's REC N-type modules experienced only 0.3% power loss after one year outdoors, while P-type modules in the same environment lost 2.1% (REC 2022 tracking report).

Calculated over a 25-year lifespan, total degradation for N-type may be 5-8% less than P-type, equivalent to about 10% more power generation.

More Stable Performance in Both Heat and Cold

The bandgap of N-type silicon (1.12eV) is slightly wider than P-type (effectively smaller due to boron-oxygen complexes), and electron mobility is also higher (1,350 cm²/V·s vs. 480 cm²/V·s for P-type).

Therefore, the temperature coefficient is -0.3%/°C, while P-type PERC is -0.35 to -0.4%/°C.

This means for every 1°C increase in temperature, N-type power drops by 0.3%, while P-type drops by 0.35-0.4%.

In Arizona, USA, where module temperatures often reach 60°C in summer (35°C above the standard 25°C), a 400W N-type module retains 8-10W more power than a P-type module (400W × 35°C × 0.05%/°C), resulting in 3-5% more annual energy generation.

Cold weather is actually beneficial; N-type power at 0°C is 5-7% higher than P-type (NREL low-temperature testing).

Higher Power Generation in Low-Light/Cloudy Conditions

NREL field tests in California found that at an irradiance of 200W/m² (one-fifth of the standard 1,000W/m²), N-type current is 5-8% higher than P-type.

The reason is the long minority carrier lifetime in N-type, allowing efficient collection of the few carriers generated under weak light.

For example, on a residential rooftop in Munich, Germany, N-type HJT modules generated 7% more power than P-type modules in November (average daily irradiance 3.5kWh/m²).

This is more pronounced in power plants in cloudy regions. A 20MW plant in the UK using TOPCon saw an additional 4.2% annual energy yield due to low-light performance.

Technology Roadmaps

TOPCon:

In 2023, it accounted for over 60% of global N-type capacity (PV Tech data) because it can be retrofitted from existing PERC production lines, saving money.

Process Steps:

5. After wafer cleaning, grow a 1-2 nanometer silicon oxide (SiO₂) layer using thermal oxidation. This layer acts like a "sieve," allowing only electrons to tunnel through (quantum tunneling effect) and blocking hole recombination.

6. Use LPCVD (Low-Pressure Chemical Vapor Deposition) or PECVD (Plasma-Enhanced Chemical Vapor Deposition) to deposit a 150-200 nanometer phosphorus-doped polysilicon layer, forming the rear-side passivated contact.

7. Use laser grooving to bring the rear electrode to the front, then print silver grid lines (20% finer than P-type, reducing shading).

Performance Parameters: Mass production efficiency 25-25.5% (Q Cells Q. TRON series measured 25.4%), bifaciality 85-90%, temperature coefficient -0.32%/°C, LID <0.5% (Fraunhofer ISE).

Cost and Manufacturers: Retrofitting a PERC line only requires adding oxidation and polysilicon deposition equipment, costing 40% less than building a new HJT line.

Representative manufacturers: Q Cells (Germany, Q. TRON series), REC (Norway, Alpha Pure-R series), Meyer Burger (Switzerland, using Schmid equipment).

Case study: The US Enel 450MW Topaz plant uses TOPCon, achieving 3.8% higher annual energy yield than PERC (Enel 2023 report).

HJT:

HJT, or Heterojunction Technology, uses an amorphous silicon and crystalline silicon stack. It has a higher theoretical efficiency ceiling than TOPCon, but equipment and materials are expensive.

Process Steps:

l Using <200°C low-temperature processes (compared to 800-900°C for PERC), first use magnetron sputtering to deposit a 5-10 nanometer intrinsic amorphous silicon (i-a-Si: H) layer to passivate surface dangling bonds.

l Then deposit a 10-15 nanometer doped amorphous silicon layer (n-type or p-type) to form the PN junction. Both sides are treated this way (for bifacial HJT).

l Print grid lines using low-temperature silver paste (200°C sintering) or directly use copper electroplating (to reduce silver paste cost).

Performance Parameters: Mass production efficiency 24.5-25% (Meyer Burger Glass-Glass modules 24.8%), bifaciality >90% (HJT can absorb light from both sides), temperature coefficient -0.29%/°C (lower than TOPCon), LID nearly 0 (no boron-oxygen complexes).

However, equipment investment is twice that of PERC (approx. $120 million/GW), and silver paste consumption is 30% higher than PERC (180mg per watt vs. 140mg).

Manufacturers and Case Studies: ENEL Green Power (Italy, uses Meyer Burger equipment), Hanwha Q CELLS (South Korea, Q. PEAK DUO series).

Case study: A farm in Bavaria, Germany, using HJT bifacial modules; the rear side contributed 22.8% of power generation (Meyer Burger 2022 monitoring).

IBC:

IBC stands for Interdigitated Back Contact. All electrodes are placed on the rear side, with no front grid lines for shading, resulting in the highest efficiency but also the most challenging manufacturing process.

Process Steps:

1. Diffuse phosphorus on both sides of the silicon wafer to form N and P regions, then use a mask to etch an "interdigitated" pattern (spacing 50-100 micrometers).

2. Evaporate a transparent conductive film (ITO) on the rear, then print silver paste electrodes (separated positive and negative).

3. Apply an anti-reflection coating (ARC) on the front side, with 2-3% higher transmittance than TOPCon.

Performance Parameters: Mass production efficiency 25-26% (SunPower Maxeon 6 reaches 25.9%), open-circuit voltage 740mV (20mV higher than TOPCon), but bifaciality is low (70%, due to rear electrode shading), and cost is 30-40% higher than PERC (complex process, difficult yield improvement).

Manufacturers and Applications: SunPower (USA, Maxeon brand, focused on premium rooftop), LG Solar (historical model NeON 2 BiFacial).

Case study: Premium residential installations in California using Maxeon 6; esthetically pleasing with no front grid lines, efficiency 25.9%, generating 5% more power than P-type of the same area (SunPower 2023 user data).

Tandem Technologies:

Stacking technologies can break efficiency ceilings, for example:

l TBC (TOPCon + IBC): Uses TOPCon passivation + IBC back contact, efficiency pushing 26.5% (Jolywood lab), but at higher cost.

l HBC (HJT + IBC): HJT's amorphous silicon passivation + IBC back contact, theoretical efficiency 29% (KAUST research), Japan's Kaneka achieved a 28.7% HBC prototype.

Comparison Table of Three Technologies (Mass Production Data)

Choosing a Path Depends on the Application

l For rapid capacity expansion and cost control: Choose TOPCon (fast PERC line conversion, suitable for utility-scale plants).

l Pursuing high bifaciality, low-temperature conditions: Choose HJT (European distributed generation, agrivoltaics).

l Premium rooftop, esthetics important: Choose IBC (no front grid lines, high premium).

P-Type Silicon Cells

P-Type silicon cells dominate ~75% of global solar capacity (2023 PV InfoLink), with PERC variants reaching 22.8% mass-production efficiency.

They cost $0.03/W less in non-silicon expenses than N-type, but face 2.5% initial light-induced degradation (LID) and a 24.5% theoretical efficiency ceiling.

Market share is projected to drop below 50% by 2025 as TOPCon/HJT expand, yet they remain critical for cost-sensitive utility-scale projects due to mature manufacturing.

Working Principle

Material Basis:

Boron is a Group III element with 3 valence electrons. When it replaces a 4-valent silicon atom in the crystal lattice, it leaves behind a positively charged "vacancy" in the crystal, which is a hole—the majority carrier in P-type material (over 90% of total carriers).

At room temperature, boron's activation energy in silicon is only 0.045 eV (NIST data), meaning almost all incorporated boron atoms can ionize to release holes, with a hole concentration reaching 10¹⁵-10¹⁶ cm⁻³ (IEA 2023 report).

In contrast, silicon's intrinsic carrier concentration is only 1.5×10¹⁰ cm⁻³ (25℃). Therefore, after boron doping, the material's conductivity is completely dominated by holes, hence the name "P-type" (positive-type).

What Happens When Light Enters:

When sunlight (AM1.5 standard spectrum, irradiance 1000 W/m²) strikes the cell surface, silicon absorbs photons with energy greater than its bandgap (1.12 eV).

The absorption coefficient varies with wavelength: Blue light (400-500 nm) is absorbed within the top 0.1 μm, red light (600-700 nm) can penetrate up to 50 μm, and infrared light (1100 nm) cannot excite electrons (limited by silicon's bandgap).

For each absorbed photon with sufficient energy, a valence band electron in silicon jumps to the conduction band, leaving a hole in the valence band, forming an electron-hole pair.

Under 1 kW/m² illumination, approximately 3×10²¹ electron-hole pairs are generated per cubic centimeter per second in silicon (calculated based on 85% quantum efficiency, IEEE Photovoltaics Journal).

How Charges Separate:

P-type silicon cells need to form a PN junction with N-type material (phosphorus-doped).

Upon contact with P-type silicon, electrons diffuse from the N-region to the P-region, and holes diffuse from the P-region to the N-region, leaving immobile ions at the interface (negative ions in P-region, positive ions in N-region), forming a depletion region.

The ionized charges in this region create a built-in electric field, directed from the N-region to the P-region, with a strength of about 10⁴-10⁵ V/cm (ISFH lab measurements).

When electron-hole pairs enter the depletion region, electrons are pushed by the electric field towards the N-region, and holes are pushed towards the P-region, achieving charge separation—this is the starting point of electricity generation.

The built-in voltage is about 0.7 V (room temperature), which sets the upper limit for the cell's open-circuit voltage.

Carrier Movement:

Majority carriers (holes in P-region, electrons in N-region) move by drift (electric field driven), while minority carriers (electrons in P-region, holes in N-region) move by diffusion (concentration gradient driven).

Diffusion length is a key parameter: The diffusion length of electrons (minority carriers) in P-type silicon Lₙ=√(Dₙτ), where Dₙ is the electron diffusion coefficient (about 35 cm²/V·s at 25℃), τ is the minority carrier lifetime (about 100-300 μs in PERC cells, JRC test data), so Lₙ is about 0.3-0.5 mm.

If carriers recombine (electrons and holes recombine) before reaching the electrodes, current is lost. Recombination mechanisms include:

l Radiative recombination: Electron-hole pairs directly release energy as light (inefficient in silicon, <1%);

l Auger recombination: Under high injection conditions, recombination energy is transferred to a third carrier (significant at high temperatures);

l Defect recombination: Impurities or dislocations in the crystal trap carriers (boron-oxygen recombination is specific to P-type, B-O pairs form recombination centers, causing initial light-induced degradation LID of about 2-3%, NREL 2022 report).

The Final Step: Current Collection

The emitter (a thin N-type layer) on the P-region surface reduces surface recombination, covered by an anti-reflection layer (silicon nitride, refractive index 2.0, anti-reflection rate >95%).

The front electrode consists of silver paste printed fine grid lines (width 30-50 μm, spacing 1-2 mm), shading about 5-8% of the area (Fraunhofer ISE data);

The rear electrode contacts through an aluminum back surface field (BSF) or PERC's passivation layer + laser-fired contacts (contact resistance <10 mΩ·cm², CEA testing).

After charges are collected by the electrodes, connecting an external load completes the circuit, generating current.

Typical PERC cell parameters: Short-circuit current Isc≈40 mA/cm², open-circuit voltage Voc≈0.68 V, fill factor FF≈82% (lab data), photoelectric conversion efficiency η=Isc×Voc×FF/Pin≈22.8% (Pin=100 mW/cm²).

Structural Evolution

First Generation (Al-BSF):

Simple four-layer structure: Front anti-reflection layer (silicon nitride, thickness 70-80nm, refractive index 2.0), emitter (thin N-type silicon layer, thickness 0.3-0.5μm, phosphorus doping concentration 10¹⁹ cm⁻³), P-type silicon bulk (thickness 180-200μm, boron doping concentration 10¹⁶ cm⁻³), rear aluminum layer (after sintering forms a P+ aluminum back surface field, thickness 1-2μm).

The aluminum back surface field (Al-BSF) acts to "block" rear-side carriers—aluminum-silicon contact forms a high-concentration P+ region at the interface (hole concentration 10¹⁸ cm⁻³), reducing electron escape from the rear (recombination reduced by about 30%).

However, clear disadvantages: No passivation layer on the rear, remaining carriers still recombine;

The aluminum layer has poor reflectivity, and long-wavelength light (1000nm) passing through the silicon wafer is absorbed by aluminum, unable to be utilized a second time.

Data: BSF mass production efficiency 17-19% (IEA 2005 report), open-circuit voltage Voc≈0.65V, short-circuit current Isc≈36mA/cm².

Wafer cost accounted for 60% of total module cost (silver paste was expensive then, 150 mg per wafer), but the process was simple—a production line cost less than $5 million (SEMI 1990 data), suitable for the early PV market.

By 2010, BSF accounted for 90% of P-type capacity, but efficiency was stuck at the 20% theoretical limit, soon replaced by PERC.

PERC:

Structure evolved to five layers: Front side still has anti-reflection layer + emitter + P-type bulk. The rear adds an aluminum oxide passivation layer (Al₂O₃, thickness 5-10nm, interface state density <10¹⁰ cm⁻²eV⁻¹, Fraunhofer ISE 2015 data) + silicon nitride capping layer (Si₃N₄, thickness 70nm, for both passivation and anti-reflection). Then, lasers create openings in the passivation layer (width 20-30μm, deep enough to reach the silicon bulk) to allow aluminum paste to contact the P-type bulk (local contact area <5%).

The passivation layer is key: The negative charge of aluminum oxide can "trap" electrons at the silicon surface (field-effect passivation), assisted by the positive charge of silicon nitride. Together, they reduce rear surface recombination velocity from 10³ cm/s for BSF to 10¹ cm/s (a 99% reduction).

Laser opening is to reduce metal contact area—BSF had full aluminum back contact, causing severe recombination; now only the openings contact, reducing recombination by 80%.

The effect is immediate: Mass production efficiency jumped from 19% for BSF to 22-23% (PV InfoLink 2023), open-circuit voltage Voc increased to 0.68V, short-circuit current Isc to 40mA/cm².

Cost? Laser equipment adds about 2 million per line, but non-silicon cost drops 0.02/W (silver paste use reduced by 20mg/wafer), so PERC capacity exploded after 2015—70% of P-type capacity in 2020, over 90% in 2023.

Current mainstream PERC cell parameters: Wafer thickness 130μm (50μm thinner than BSF), silver paste consumption 100mg/wafer (NREL 2022), temperature coefficient -0.45%/℃, suitable for ground-mounted power plants in places like Texas, USA, and Spain with strong sunlight and large temperature swings.

Third Generation (PERT/PERL):

PERT (Passivated Emitter Rear Totally-diffused) and PERL (Passivated Emitter Rear Locally-diffused) are "fine-tuned" versions of PERC, aiming to reduce series resistance.

Structurally, the rear passivation layer remains, but the full aluminum back surface field is replaced with a localized heavily doped region—using photoresist as a mask, only the opening locations undergo high-concentration phosphorus diffusion (N+ region, thickness 0.5μm), while the rest remains P-type bulk.

Thus, contact resistance drops from 10 mΩ·cm² for PERC to 5 mΩ·cm² (CEA 2018 testing), fill factor FF increases from 82% to 84%.

PERL is more extreme: Full heavy doping diffusion on the rear (full N+ back surface field), but isolated with an ultra-thin oxide layer (SiO₂, thickness 1nm) to reduce metal contact recombination.

Efficiency can reach 23.5% (lab, ISFH 2020), 0.5% higher than PERC.

But the problem: Photoresist masking + two diffusion steps add 3 more process steps, requiring an additional $3 million investment per line (SolarPower Europe 2021), and yield drops from PERC's 98% to 95%.

Therefore, as of 2023, PERT/PERL capacity is less than 5% of P-type, only used in small batches in premium modules like Japan's Sharp and Germany's Q Cells.

Advantages and Limitations

Advantages:

Lower cost: Boron is cheaper than phosphorus, savings in both wafers and non-silicon materials

P-type silicon cells use boron doping. Boron source prices are 70% of phosphorus sources (IEA 2023 mineral report).

The boron doping process is mature, wafer production costs are 10-15% lower than N-type—e.g., M6 size (166mm) P-type wafer cost 0.18/piece, N-type phosphorus-doped wafer 0.21/piece (PV InfoLink 2023Q3).

Non-silicon costs are also lower: Silver paste consumption is about 100mg/wafer (NREL 2022), 25% more than N-type TOPCon's 80mg, but boron doping allows for a thinner aluminum paste back field, resulting in overall non-silicon cost per watt $0.03 lower than N-type.

Processes require minimal changes; old production lines can be upgraded

P-type PERC technology can be directly retrofitted on old BSF production lines: add a laser grooving machine (200,000/unit) and aluminum oxide passivation layer deposition equipment (500,000/line).

Total modification cost is less than 60% of building a new N-type TOPCon line.

For example, a German factory retrofitted its BSF line to PERC in 2018, started production in 3 months, increased capacity from 200MW to 500MW, with an investment of only $8 million.

Mass production is stable, yield is high, suitable for large-scale projects

P-type cells have 30 years of industrial history, with yields stable above 98%.

A 1GW ground-mounted power plant in Nevada, USA, using PERC modules showed only 2.1% degradation after 5 years of operation (NREL tracking data), 0.5% lower than early N-type projects.

Utility-scale plants in Europe (Spain, Italy) prefer P-type due to lower cost—in 2023, P-type module winning bid price was 0.22/W, N-type 0.25/W (PV Tech bidding data), a difference of 3 cents per watt, saving $30 million on a 1GW project.

Limitations:

Efficiency plateaued early, theoretical ceiling is a bottleneck

P-type silicon has inherently short minority carrier lifetime, and boron-oxygen complexes (B-O pairs) cause initial light-induced degradation (LID).

PERC lab efficiency maxes at 24.06% (ISFH Germany, 2022), theoretical limit 24.5%;

N-type HJT lab efficiency has reached 26.81% (LONGi USA, 2023), a 2+ percentage point difference.

In mass production, P-type PERC efficiency 22-23%, N-type TOPCon 24-25%, a per-watt power difference of 15-20W.

Power output drops faster in heat, temperature coefficient is less favorable

P-type cell temperature coefficient is -0.45%/℃, 80% higher than N-type HJT's -0.25%/℃.

In Rajasthan, India (summer 45℃), P-type module noon power is 18% lower than rated, N-type only 11% lower, resulting in an additional daily loss of 0.07kWh/W (NREL simulation).

Data from Arizona, USA, PV projects show P-type annual energy yield is 5-7% lower than N-type (First Solar report).

Wafers are brittle when thin, thinning is difficult to advance

P-type silicon wafers have low mechanical strength. 130μm is the current mainstream thickness (was 180μm in 2015).

Reducing to 120μm increases breakage rate from 1% to 5% (IEA 2023 thinning report).

N-type wafers at the same thickness have only a 2% breakage rate because phosphorus-doped crystals are denser.

120μm P-type wafers yield 62 pieces per kg, 110μm N-type yield 68 pieces per kg, 6 more pieces per kg, reducing silicon cost by 8% (SEMI estimate).