How to Design Solar Photovoltaic Modules | 3 Steps

Designing a photovoltaic module requires first selecting monocrystalline silicon cells with an efficiency of 18%-23% and connecting them in series and parallel to form the required voltage and current, then performing EVA encapsulation and tempered glass lamination, and finally testing to control the power deviation within ±3% to ensure stable output.

Cell Selection and Electrical Sizing

Choosing the Size

Mass-produced N-type monocrystalline silicon wafers are divided into two edge length specifications: 182 mm and 210 mm. Using M10 specification wafers with a 182 mm edge length, the diagonal length is 247 mm, and the physical area of a single wafer reaches 330.15 square centimeters. Using G12 specification wafers with a 210 mm edge length, the single wafer area expands to 440.96 square centimeters. The thickness of the wafers is generally cut to between 130 microns and 110 microns, and the thickness tolerance must be controlled within plus or minus 5 microns.

To reduce the internal resistance loss of a single cell, the complete 182 mm cells are laser-cut into 182 mm by 91 mm half-cells, and the 210 mm cells are cut into 210 mm by 105 mm half-cells. The laser cutting depth is set to one-third of the wafer thickness, which is about 40 microns, and the heat-affected zone width must be less than 50 microns.

The mass-produced average photoelectric conversion efficiency of N-type TOPCon monocrystalline cells is stable in the range of 25.2% to 25.8%, with their first-year Light-Induced Degradation (LID) rate suppressed below 1.0%, and the annualized degradation rate from the second to the twenty-fifth year controlled within the range of 0.35% to 0.40%. The anti-reflective coating on the front surface of the cell is made of silicon nitride, with a thickness set at 75 nm to 85 nm, which can reduce the visible light reflectance of wavelengths from 400 nm to 1100 nm to below 1.5%.

Matching the Voltage

After selecting the 182 mm half-cells, 144 half-cells are connected in series according to their physical sequence via tin-plated copper ribbons to form a complete electrical circuit. The nominal open-circuit voltage of a single N-type TOPCon cell under Standard Test Conditions (STC) (25°C, 1000 W/m²) is 0.715 V to 0.725 V, and the maximum power point voltage is about 0.61 V.

l Dividing the 144 half-cells into two parallel sections, with 72 cells connected in series per string, the total open-circuit voltage of the entire module theoretically stacks up to 51.4V to 52.2V, and the maximum power point operating voltage falls in the range of 43.9V to 44.5V.

l The open-circuit voltage temperature coefficient of the cells is -0.24%/°C to -0.26%/°C. When the system operates in a low-temperature environment of minus 40°C, the open-circuit voltage of a single module climbs from 51.8 V at 25°C to about 60.5 V.

l Commercial and utility-scale photovoltaic power plants adopt a system DC voltage upper limit setting of 1500 V.

l Calculated based on the low-temperature extreme open-circuit voltage of 60.5 V, a single branch of a DC combiner box is allowed to connect a maximum of 24 modules in series, reaching a total voltage of 1452 V, reserving a 48 V electrical safety margin.

Calculating the Current

The setting of current parameters depends on the effective light-receiving area of the silicon wafer and the series-parallel structure. Under a light intensity of 1,000 W/m², the short-circuit current of a complete 182 mm specification cell reaches 13.8 A to 14.2 A, and the short-circuit current after being cut into half-cells is halved to 6.9 A to 7.1 A.

l The 144 half-cells inside the module adopt a layout of 72 series and 2 parallel. The total short-circuit current at its output end stabilizes between 14.0A and 14.3A, and the maximum power point operating current maintains a level of 13.1A to 13.4A.

l The short-circuit current temperature coefficient is +0.045%/°C to +0.050%/°C. In a high-temperature operating environment of 65°C, the short-circuit current of the module rises by about 1.8%, reaching 14.5 A.

l The single-channel MPPT (Maximum Power Point Tracking) rated input current of the inverter must match this parameter; the single-channel DC input current upper limit of a commercial string inverter is set at 16A or 20A.

l When a certain cell is shaded by leaves or dust to form a hot spot effect, the 3 Schottky bypass diodes in the junction box will automatically conduct.

l For the 14.5A operating current, the rated forward conduction current of the bypass diodes is selected at the 25A to 30A specification, with the upper limit of the diode junction temperature reaching 200°C.

Wiring Connections

The electrical connection between cells relies on Super Multi-Busbar (SMBB) interconnection technology. The front and back sides of N-type cells are printed with 16 or 18 busbars, and the silver paste consumption per cell is compressed to 80 mg to 95 mg. The circular tin-plated copper ribbon used to connect these busbars has a diameter of 0.25 mm to 0.30 mm.

l A 550W module containing 144 half-cells consumes 120 meters to 130 meters of interconnecting ribbon, and the total weight of the ribbon is about 350 grams.

l The yield strength of the interconnecting ribbon is controlled between 60 MPa and 80 MPa, with an elongation greater than 20%, absorbing the 2 mm to 3 mm deformation tension generated by the module during thermal expansion and contraction cycles from minus 40°C to 85°C.

l The layout spacing between cells is set to 1.5 mm to 2.0 mm, and the total internal resistance of the entire series circuit is controlled within the range of 0.35 ohms to 0.45 ohms.

l Under an operating current of 13A, the 0.4-ohm internal resistance generates about 67.6W of Joule heat loss, accounting for about 12.2% of the module's 550W total output power; optimizing the cross-sectional area of the ribbon reduces the line loss ratio by 0.5% to 0.8%.

Testing Degradation

After completing the electrical topology design, derating calculations are performed on the module's output parameters. A standard photovoltaic module passes a 600-hour damp heat test (85°C environment, 85% relative humidity) and 200 cycles of thermal cycling tests (minus 40°C to 85°C).

l After the test, the module's power degradation rate is less than 5.0%, and the increase in series resistance does not exceed 10% of the initial value.

l In the leakage current test under 1500V DC high voltage, the leakage current within 1 minute does not exceed 10 microamps per square meter, and the total leakage current is less than 50 microamps.

l Calculated based on the global average manufacturing cost of $0.12 to $0.15 per watt, the ex-factory material and labor cost of a single 550W module ranges from $66 to $82.5.

l For every 0.1% increase in the single-cell photoelectric conversion efficiency, the output power of the entire module increases by about 2.5 W. Over a 25-year lifecycle, under 2000 hours of annual equivalent utilization, it generates an extra 500 degrees (kWh) of electricity, yielding an additional $25 in electricity revenue calculated at an average on-grid tariff of $0.05 per kWh.

Circuit Layout and Interconnection

Layout and Routing

In the module layout of 144 half-cells, the layout routing sets the physical transmission track for the 550W rated power. The 144 half-cells are evenly divided into 6 series groups, with each group containing 24 monocrystalline silicon half-cells. The 6-by-24 matrix arrangement adopts a U-shaped loop design, with the overall covering length reaching 2,278 mm and the width occupying 1,134 mm.

In the longitudinal arrangement, the physical spacing between the upper and lower cells is set to 1.2 mm to 1.5 mm. A busbar safety distance of 2.5 mm to 3.0 mm is left between two adjacent cell strings in the transverse direction. The insulation distance from the module edge to the outermost cells is strictly controlled between 12 mm and 15 mm to resist surface creepage phenomena caused by 1500 V system high voltage at 85°C.

To suppress the series current mismatch rate below 0.1%, the short-circuit current difference among the 24 cells within the same string is limited to within 0.05 A during the sorting process. When light is projected onto the surface, the top 72 cells and the bottom 72 cells form two independent parallel circuits, and the short-circuit currents of both the top and bottom halves can hit the full-load value of 14.2A.

Selecting the Ribbon

Electrical interconnection heavily relies on the circular tin-plated copper ribbons in Super Multi-Busbar (SMBB) technology. An N-type half-cell surface has an average of 16 to 18 silver busbars distributed with a width of 30 microns to 40 microns. The diameter of the circular ribbon attached to the silver lines is compressed by the wire drawing process to 0.26 mm to 0.32 mm.

The outer layer of the copper ribbon is wrapped with a 15-micron to 20-micron thick tin-lead-silver alloy coating, with a ratio usually at 62% tin, 36% lead, and 2% silver. The addition of 2% silver accurately locks the melting point of the solder at 179°C.

Inside the infrared stringing machine, the ribbon passes through a 120°C preheating zone for 10 seconds, and then enters a 210°C to 230°C peak soldering zone, where the residence time is only 2.2 seconds to 2.5 seconds. After cooling, the peel force between the ribbon and the cell surface reaches 1.5 N/mm to 2.0 N/mm. The total ribbon usage for a single 144-format module reaches 125 meters, consuming a pure copper weight of about 340 grams to 360 grams, and the corresponding material procurement cost per module fluctuates between $1.2 and $1.5.

Calculating Expansion Deformation

Leaving precise millimeter-level gaps can absorb the massive thermal expansion coefficient differences between different materials. The thermal expansion coefficient of a monocrystalline silicon wafer is 2.6×10^-6/K, while the expansion coefficient of copper wire is as high as 16.5×10^-6/K.

When the outdoor ambient temperature climbs from minus 40°C to 85°C, an extreme temperature difference of 125°C is generated. Under the huge temperature span of 125°C, the 1.5 mm suspended copper ribbon connecting two cells will produce about 0.18 mm of elongation deformation.

If the cell spacing is excessively compressed to below 0.8 mm, the thrust generated by the thermal expansion of the ribbon will reach 3 Newtons to 5 Newtons, which has a high probability of causing micro-cracks over 50 microns long at the edge of the silicon wafer. On a high-speed stringing assembly line passing 3000 cells per hour, if the hidden crack scrap rate caused by mechanical stress exceeds 0.2%, the monthly wafer loss expense for a single 500MW production line will exceed $45,000.

Calculating Losses

The assembly process from single cells to complete finished products is accompanied by the physical interplay of the CTM (Cell to Module) power conversion ratio. Interconnecting ribbons with a circular cross-section secondarily refract more than 50% of the incident light back to the upper glass-air interface at a reflection angle of 60 to 80 degrees.

The reflected light eventually forms total internal reflection and hits the effective light-receiving surface of the underlying silicon wafer again, bringing an additional optical power gain of 2.5% to 2.8%.

When a 13.5 A DC flows through the 125-meter-long interconnected copper wires and busbars, the equivalent series resistance of the entire metal circuit is about 0.42 ohms. Calculated according to Joule's law, the pure resistance power loss caused by wire heating reaches about 76 W. The optical gain above compensates for the current loss below, forcefully pulling the module's final CTM encapsulation loss rate back into a narrow range of 1.5% to 2.0%.

Connecting Junction Box Leads

The bus current passes through tin-plated copper leads with a width of 5 mm to 6 mm and a thickness of 0.3 mm, going through strip-shaped holes reserved on the insulating backsheet, and connecting to the three-part split junction box.

Inside the three independent plastic junction boxes, a Schottky bypass diode with a maximum withstand current of 30A is encapsulated in each. The forward voltage drop of the diode is strictly capped at 0.45V to reduce the heat generated during high-current conduction.

The junction box uses a PPO engineering plastic housing with an insulation level reaching 1000MΩ, and its waterproof and dustproof rating complies with the IP68 test specifications. The factory's automated dispensing machine injects 18 ml to 22 ml of A/B two-module silicone into the plastic box for potting and wrapping.

The liquid silicone fully cures after sitting for 45 minutes at a room temperature of 25°C. The thermal conductivity after curing must exceed 0.8 W/(m·K). The junction box extends outward with photovoltaic-specific DC cables having a cross-sectional area of 4.0 square millimeters (roughly equivalent to 12 AWG specification), and the lengths of the positive and negative cables are cut to 300 mm or 1,200 mm as required.

The halogen-free cross-linked polyolefin insulated cables have a conductor DC resistance of less than 5.09 ohms per kilometer under a continuous operating temperature of 90°C.

Encapsulation and Framing

Laying Encapsulant Film

Laying encapsulant film with a thickness of 0.45 mm to 0.60 mm is the physical defense line to prevent water vapor penetration. For N-type bifacial cells, the front side is usually laid with a transparent POE film having a basis weight of 420 to 460 grams per square meter, with transmittance stable in the range of 91.5% to 92.5%.

The back side is laid with high-reflective white EVA film with a basis weight of 400 grams per square meter, reflecting light that penetrates the physical gaps between cells back to the light-receiving surface, bringing about a 1.2% to 1.5% short-circuit current gain. The shrinkage rate of the film at a room temperature of 25°C must be strictly controlled to less than 1.5% in the longitudinal direction and less than 1.0% in the transverse direction to prevent physical deformation exceeding 2 mm at 150°C high temperatures, which could lead to cell string displacement or interconnection ribbon breakage.

In the wavelength range of 380 nm to 1100 nm, the ultraviolet (UV) cutoff wavelength of the 0.45 mm thick POE film is set between 280 nm and 320 nm, allowing visible light to fully pass through while pushing down the Yellowness Index (YI) caused by long-term UV exposure to below 3.0 after a 3000-hour UV aging test.

Applying the Glass Plates

Both the upper and lower sides of the encapsulant film are covered with 2.0 mm thick semi-tempered patterned glass. For a module with external dimensions of 2,278 mm by 1,134 mm, the weight of a single piece of 2.0 mm glass reaches 12.8 kg, and the dual-glass structure pushes the frameless base weight of the entire module up to about 27.5 kg. The iron content of the glass body itself must be below 0.012% for the transmittance parameters to meet the industrial scope of ultra-clear patterned glass.

The glass surface is coated with a 100 nm to 120 nm thick porous silicon dioxide anti-reflective (AR) coating via a roll coating process. The coating reduces the light reflectance across a broad spectral range from 4.0% to about 2.5%, increasing the output power of the complete finished module by approximately 2.0% to 2.5%. The semi-tempering treatment maintains the surface stress of the glass between 90 MPa and 110 MPa, and the fragmentation state after suffering a heavy impact will not exceed 40 pieces within a 50 mm by 50 mm area.

Vacuum Evacuation

The 5-layer sandwich assembly—composed of the dual-glass, polymer encapsulant films, and 144 half-cell strings—is fed into a dual-layer heated vacuum laminator. The temperature of the lower heating plate of the laminator is stabilized for a long time within a narrow range of 145°C to 152°C. The first stage of lamination is a vacuum evacuation process lasting 5 to 6 minutes; the air pressure inside the chamber rapidly drops at a rate of 20 Pa to 30 Pa per second until the absolute pressure is below 80 Pa.

The massive air pressure difference forcefully extracts the free air trapped between the multiple layers of materials, as well as the trace amounts of low-molecular silane coupling agent gases volatilized from the heated encapsulant films. If the absolute pressure during this stage is higher than 100 Pa, tiny bubbles exceeding 0.5 mm in diameter will form inside the cured transparent film, which can easily trigger large-scale physical delamination and insulation failure during the subsequent 25 years of outdoor sun exposure.

The system pressure during the pressurization stage is maintained at 0.7 to 0.8 standard atmospheres, and the physical pressure exerted on the dual-glass surface is about 70 kPa to 80 kPa, with a continuous holding time set to 10 to 12 minutes. After the high-temperature and high-pressure cross-linking reaction at 150°C, the gel cross-linking degree of the EVA film reaches 80% to 85%, and the cross-linking degree of the POE film must exceed 75%.

Trimming the Excess

The surface temperature of the module exiting the laminator is as high as 110°C to 120°C, and it is fed by a track onto an air-cooled conveyor belt, taking 8 to 10 minutes to forcibly cool down to below 45°C. After cooling, it enters a fully automatic edge trimming process. Because the film will spill out to the surroundings when pressurized at a high temperature of 150°C, cured adhesive strips of varying widths from 2 mm to 5 mm will remain on the glass edges.

A robotic arm equipped with a high-temperature hot-melt cutter at 180°C to 200°C performs edge-to-edge cutting along the physical edges of the dual-glass at a high speed of 150 mm to 200 mm per second. The trimming tolerance is limited to within plus or minus 0.5 mm by an industrial-grade machine vision system. If the spilled adhesive is not cut cleanly, the liquid silicone will not be able to form a dense, waterproof bonding surface with the glass edges during frame assembly. The insulation resistance of the trimmed module must remain above 400 megohms under the application of 1500V DC high voltage.

Dispensing Sealant

Before framing, a fully automatic two-module dispensing machine is used to evenly inject dealcoholized room-temperature-vulcanizing (RTV) silicone rubber into the U-shaped groove of the aluminum alloy frame. The injection volume per meter of the frame is strictly set between 14 grams and 18 grams, and the cross-sectional area of the adhesive strip is about 8 to 10 square millimeters. The viscosity of the silicone rubber during extrusion is maintained at 60,000 mPa·s to 80000 mPa·s; the sufficient viscosity ensures that no gravity sagging occurs during vertical application.

The anodized aluminum alloy frame loaded with liquid silicone is fitted onto the glass edges via a pneumatic lifting device, and the corner keys at the four top corners are instantly locked tight with a stamping force exceeding 800 kg. The liquid silicone produces a dry surface skin after resting for 2 hours in a factory environment with a room temperature of 25°C and a relative humidity of 50%. Complete deep curing takes 24 to 48 hours. After curing, the Shore hardness reaches 40A to 50A, and the elongation at break exceeds 300%.

Load Bearing Pressure Test

The fully encapsulated finished product needs to pass rigorous mechanical load physical tests. The wall thickness of the 30 mm or 35 mm thick aluminum alloy frame is usually set to 1.2 mm to 1.5 mm; its tensile strength needs to reach the passing mark of 150 MPa, and the yield strength falls in the range of 110 MPa to 130 MPa.

The front of the module is evenly stacked with simulated static load sandbags equivalent to a pressure of 5400 Pa for a duration of 1 hour, used to simulate the heavy pressure of snow accumulation over 0.5 meters thick in extremely cold regions. A dynamic negative pressure suction test of 2400 Pa is applied to the back side, simulating the outward pulling force generated by a Category 12 hurricane with wind speeds up to 130 km/h. After 3 complete cycles of alternating positive and negative pressure tests, the micro-crack increase rate of the 144 half-cells inside the module must be lower than 2.0%, and the overall output power degradation rate cannot exceed 5.0%.